The present invention relates to a data processor including a central processing unit and a data transfer control device, and more particularly to technology effectively applied to data block transfer (burst transfer).
The Japanese Unexamined Patent Publication No. 2001-154977 describes a data transfer controller having dual address mode. The data transfer controller has buffers of plural stages and a counter, and includes a data buffer circuit that can input and output data in the first in, first out mode in response to counting operation of the counter. Since the data buffer circuit has buffers of plural stages, in dual address mode, with the number of stages of buffers as an upper limit, data can be continuously read from a transfer source address and stored in the data buffer circuit, and the stored data can be continuously written to a transfer destination address. In the dual address mode, a read and a write may not be alternately performed. For this reason, data transfer efficiency can be increased in SDRAM (synchronous DRAM) and other devices capable of continuous data input-output operation such as burst access during which memory cells with common row addresses are continuously accessed while column addresses thereof are sequentially switched.
Japanese Unexamined Patent Publication No. Hei 3(1991)-134750 describes technology for supporting single mode and page mode when a DRAM controller is provided with a memory capable of holding plural pieces of word data. Japanese Unexamined Patent Publication No. Hei 11(1999)-85670 describes a microcomputer in which DMAC is provided at a preceding stage of a bus controller and the need for DMAC buffer is eliminated.
The inventor has found the following problems as a result of further investigation of DMAC (Direct Memory Access Controller). First, when USB (universal serial bus) interface is to be used for data transfer, if DMAC attempts to read the FIFO buffer beyond the empty state thereof, the value of address pointer of the FIFO buffer may be destroyed.
Second, when transfer addresses are odd addresses or the number of pieces of data to be transferred is odd, transferring all the data on a byte basis, which is a minimum unit of data transfer, would deteriorate data efficiency.